Why do we need a lock prefix before CMPXCHG

Question

why do we need a lock prefix before CMPXCHG in intel architecture. see link http://courses.engr.illinois.edu/ece390/archive/spr2002/books/labmanual/inst-ref-cmpxchg.html

that I’m not sure what the consequences are if not to use a lock. because between loading a value in eax and LOCK CMPXCHG exception, the value can be changed regardless of the lock prefix, because the loading value in eax and LOCK CMPXCHG are two instructions.

To say if I do not use CMPXCHG, the worst thing that can happen is that I need to spin again.

Answer 1

• CMXCHG truly atomic (asserts bus lock) in a multiprocessor system only when it has the LOCK prefix. These days, protocol-based caching coherence protocols are used that eliminate the need for fencing (bus lock).
• Returning to the second part of the question (the value will be changed in any case). YES in this case, the CMPXCHG command fails, but nonetheless is still atomic with respect to all processors.

Bottom line : the lock prefix makes the CMPXCHG command for the multiprocessor barrier command.