Is there a Perl lesson for Verilog engineers?

Question

I want to start learning Perl, in particular, for checking verilog output files. Is there some kind of tutorial specifically designed for Perl for Verilog engineers or something like that?

Answer 1

I'm afraid I don’t know anything about Verilog either, although I note that CPAN has Verilog Distribution and it contains many modules that may be relevant to your work. Doing a search on search.cpan.org may also bring some benefits.

In any case, you need to learn how to walk before you can run. This is great to have a goal when learning a new language, but modules will not help you if you are not the first to understand the syntax and semantics of Perl.

If you are looking for a good book to learn, then the already mentioned Learning Perl (by Stackoverflow Regular brian d foy) is excellent; grab the latest version you can find. If you want to start learning right now, I would recommend downloading Perl Training Australia Perl Programming Course . Both resources contain many detailed examples, links to additional information and exercises that you can try to strengthen your knowledge.

There is also a list of recommended online lessons on the Perl 5 wiki .

Disclosure: I am a co-author of Perl Training Australia tutorials, and I admire brian d foy as one of the heroes of the Perl community. I am also a random contributor to the Perl 5 wiki.

All the best

Floor

Answer 2

I don't know anything about Verilog, but if you are already familiar with another programming language, I highly recommend learning Perl.

You can also check this page for future reference.

Answer 3

I'm not sure about the parsing of the output (you should be most specific as to how it looks), but there seems to be a good guide to the existing Verilog modules that have been recently updated.

Answer 4

Perl Intro on perldoc is how I first learned about it. This is a very quick and easy language overview. All beginners who already know the programming language should start here. You can read it in about half an hour and be ready to start coding.

Answer 5

Verilog gate-level netlist files are simply text files that are usually output from some software, such as Synopsys Design Compiler, and are therefore well suited for Perl analysis.

Being simple text files, there is nothing special about Perl. Check out any Perl tutorial that talks about the basics of Perl syntax and regular expressions, and what you learn should be easy to adapt to your Verilog tasks. See For example: http://perldoc.perl.org/perlintro.html for a general introduction. http://perldoc.perl.org/perlretut.html - for a good regular expression tutorial.

However, even a simple program can have many hidden errors. For example, let's say you want to print all the module names from the Verilog hierarchical netlist:

use strict; use warnings; my $infile = $ARGV[0] or die "$0 Usage:\n\t$0 <input verilog file>\n\n"; open(my $in_fh , '<' , $infile) or die "$0 Error: Couldn't open $infile for reading: $!\n"; while(<$in_fh>) { if (m/^module\s+(\S+)/) { print "$1\n"; } } close($in_fh) or die "$0 Error: Couldn't close $infile after reading: $!\n"; 

Even this short example is full of potential errors: what if the module name does not match the keyword "module"? what if between the opening “no” (“module” and “module name”, what if there is a space (or spaces) between the beginning of the line and the keyword “module”?

You need to know these problems. If you only need a one-time solution for a specific Verilog-related task, a simple Perl script such as the aforementioned solution is a good solution providing proper documentation to warn future users of their known flaws.

If you need something more complex related to more complex Verilog code analysis, I would try to find out if any of your existing tools (compiler, linter, formal equivalence checker, simulator, etc.) provide you access to data you need. All of these tools include mature and working Verilog guerrillas optimized for speed / memory and often provide a Tcl interface for accessing data.

Some of the above people recommended Verilog-Perl. I tried this and found it to be very slow. If you work with netlists over 100 MB, I would not use this solution, but your mileage may vary.

Answer 6

I believe you are looking for Verilog Perl . For the Perl billing class for Verilog / VHDL, view this from Doulos . This is the second time I have voted Perl Training Australia to teach Perl programming to learn Perl in general.

Answer 7

You can find it in the perl section of http://pickatutorial.com