Simple makefile file generation utility?

Question

Does anyone know a tool that generates a makefile by scanning a directory for source files?

It may be naive:

• no need to define external dependencies
• use default compiler / linker settings.

Answer 1

You can write a Makefile that does this for you:

 SOURCES=$(shell find . -name "*.cpp") OBJECTS=$(SOURCES:%.cpp=%.o) TARGET=foo .PHONY: all all: $(TARGET) $(TARGET): $(OBJECTS) $(LINK.cpp) $^ $(LOADLIBES) $(LDLIBS) -o $@ .PHONY: clean clean: rm -f $(TARGET) $(OBJECTS) 

Just put this in the root directory of the source hierarchy and run make (you'll need GNU Make for this to work).

(Note that I do not own the text Makefile ish, so it may be easier to do.)

Answer 2

CMake does this, and it even creates Visual Studio make files and projects. http://www.cmake.org/

All you have to do is create a CMakeLists.txt file containing the following lines:

 file(GLOB sources *.h *.c *.cxx *.cpp *.hxx) add_executable(Foo ${sources}) 

Then go to a clean directory and enter:

 cmake /path/to/project/ 

This will create make files in this clean build directory.

Answer 3

This is what I would use for a simple project:

 CC = $(CXX) CXXFLAGS += -ansi -pedantic -W -Wall -Werror CPPFLAGS += -I<Dir Where Boost Lives> SOURCES = $(wildcard *.cpp) OBJECTS = $(patsubst %.cpp,%.o,$(SOURCES)) all: myApp myApp: $(OBJECTS) 

The only limitation is that if you create the myApp executable. Then one of the source files should be named myApp.cpp (where I put main).

Answer 4

There is a very old script called "makedepend" that was used to create very simple makefiles. I have since switched to cmake for almost everything.

Here's the wiki article http://en.wikipedia.org/wiki/Makedepend , take a look at the list of alternatives below, including depcomp in automake, and the -M flag in NCA.

EDIT: as someone pointed me to another question, gcc -MM *.cpp > Makefile creates a pretty nice simple makefile. You only need to add your CPPFLAGS and the rule to build the entire binary ... which will take the form:

 CPPFLAGS=-Wall LDFLAGS=-lm all: binary_name binary_name: foo.o bar.o baz.o biff.o 

Answer 5

• no need to define external dependencies
• use default compiler / linker settings.

Why is the script then? If all the project source files are *.cpp and in the current directory:

 all: $(notdir $(CURDIR)) $(notdir $(CURDIR)): $(subst .cpp,.o,$(wildcard *.cpp)) $(LINK.cpp) $^ $(LOADLIBES) $(LDLIBS) -o $@ 

The Makefile will create all source files with default compiler / linker settings in an executable file with a name after the name of the current directory.

Otherwise, I usually recommend that people try SCons instead of doing where it is much simpler and more intuitive. Added bonus that there is no need to manually encode clean targets, source and header dependency checking is built-in, it is recursive and supports libraries properly.

Answer 6

As described in a related discussion, HWUT is a tool that can generate pretty Make files, look for dependencies, and include files in directories that you tell it to. In windows you need to install MinGW and Ctags. On Linux, most likely gcc and ctags are present. It is an open source and free to use.

In particular, when creating unit tests for some existing modules of any larger project with poor adhesion, this function easily saves you hours or even days.