A conditional variable defines in a Makefile with ifeq

Question

I am trying to define variables in a Makefile according to conditions. Since ifeq can only be run in rules, I added an additional rule (def_rule), which I name for each rule.

Example:

def_rule: ifeq ($(TARGET), android) CC=arm-linux-androideabi-gcc else echo "native build" endf all: def_rule tp xi_eid_chipset.o 

Unfortunately, the make call does all of this:

ifeq (linux, android)
/ bin / sh: Syntax error: word unexpected (pending ")")
make: *** [def_rule] Error 2

I can’t understand why. I just gave examples in the GNU Make documentation.

Do you know how to execute conditional definitions in Make files?

Answer 1

Conditional may be outside the rules:

 ifeq ($(TARGET), android) $(info Android) CC=arm-linux-androideabi-gcc else $(info native build) CC=something else endif 

(Note that I threw in several leading places, just to make it easier to read - they are neither necessary nor harmful.)