If the high bits N
virtual address are zero, then the translation starts with TTBR0
else TTBR1
. N
comes from TTBCR
. The TTBRn
registers contain the physical address of the base of the first level table. The corresponding record of the first level table is loaded, and the various bits of the record determine whether the translation uses the second level table, and if so, what is its physical address.
In the MMU, you can configure the use of short descriptors (32-bit physical addresses) or long descriptors (40-bit physical addresses). When using short descriptors, no more than two levels of the translation table can be used. When using long descriptors, there can be three levels.
This ignores the transitions of the second stage (hypervisors). Everything is described in ARMARM for the V7-A & R B3.3 section: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html
scott
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