How many bytes does the cache controller retrieve time from main memory in L2 cache?

Question

I just read two articles on this topic that provide information inconsistently, so I want to know which one is correct. Perhaps both are correct, but in what context?

first says we get page size time

The cache controller always monitors the loaded memory cells and loads data from several memory positions after the memory position that has just been read.

To give you a real-world example, if the CPU has loaded the data stored at address 1000, the cache controller will download data from the "n" addresses after address 1000. This number "n" is called the page; if this processor works with 4 KB pages (which is a typical value), it will load data from 4096 addresses below the current current memory position (address 1000 in our example). The following figure shows this example.

second says we get sizeof (cache line) + sizeof (prefetcher) time

So, we can summarize how the memory cache works:

• The processor requests the instruction / data stored at address "a".
• Since the contents of address “a” arent inside the memory cache, the CPU must retrieve it directly from RAM.
• The cache controller loads a line (usually 64 bytes), starting with address "a" in the cache memory. This is more data than the requested CPU, therefore, if the program continues to run sequentially (i.e., requests the address a + 1), the next command / data that the processor will request will already be loaded into the memory cache.
• A schema called prefetcher loads more data located after this line, i.e. starts loading content from address a + 64 into the cache. To give you a real-world example, Pentium 4 processors have a 256-byte prefetcher, so it loads the next 256 bytes after the line already loaded into the cache.

Answer 1

It completely depends on the hardware implementation. Some implementations load one line from main memory at a time; and cache line sizes vary greatly between different processors. I have seen row sizes from 64 bytes to 256 bytes. Basically, the size of the "cache line" means that when the CPU requests memory from the main RAM, it does this by n bytes at a time. Therefore, if n is 64 bytes, and you load a 4-byte integer into 0x1004, the MMU will actually send 64 bytes on the bus, all addresses from 0x1000 to 0x1040. This entire piece of data will be stored in the data cache as a single line.

Some MMUs can retrieve several cache lines on the bus for each request, so a request to the address 0x1000 on a machine with 64 byte caches actually loads four lines from 0x1000 to 0x1100. Some systems allow you to do this explicitly with special prefetch codes or DMA codes.

However, the article on your first link is completely incorrect. It confuses the OS size of the memory page with the hardware cache line . These are completely different concepts. The first is the minimum size of the virtual address space that the OS will allocate immediately. The latter provides detailed information on how the processor interacts with the main RAM.

They are similar to each other only in the sense that when the OS does not work much in physical memory, it will output some recently used virtual memory to disk; and then when you use this memory again, the OS loads the entire page from disk back into physical RAM. This is similar (but not related) to the way the processor loads bytes from RAM, so the author of Secrets of Hardware was confused.

A good place to learn all about computer memory and why caches work the way they do is Ulrich Drapper's paper. What every programmer should know about memory .