A few days ago, I posted a response to a stack overflow on how to write a hierarchical make (http://stackoverflow.com/questions/1498213/make-hierarchical-make-file). The answer has been deleted, so I assume it was completely incorrect or not relevant to the topic (or both).
I would like to know how to write a hierarchical Makefile. This is a Makefile that calls several Makefiles in subdirectories. I assume a directory structure such as:
- project |--module1 |--Makefile |--... |--module2 |--Makefile |--module2.1 |--module2.2 |--... |--module3 |--Makefile |--... |--etc
I also assume that the project participants agreed with only a minimal set of target makefiles, such as: all (default), clean, install, etc. Thus, the following modules, including make flags, will be distributed to the modules:
cd project make clean make -k make install
What happened to the following Makefile project:
PACKAGES = \ module1 \ module2 \ emodule3 VIRTUAL_PACKAGES = $(addsuffix /.virtual.Makefile,${PACKAGES}) TARGETS=clean install all .PHONY: $(TARGETS) default: all FLAGS = $(ifeq $(MAKEFLAGS) "","",-$(MAKEFLAGS)) $(TARGETS): $(VIRTUAL_PACKAGES) $(VIRTUAL_PACKAGES): $(MAKE) $(FLAGS) -C $(@D) $(MAKECMDGOALS)
yes, $ VIRTUAL_PACKAGES in the Makefile looks weird. The alternative to mixing the for loop is a little shorter, but I'm not sure if this is better (since I need to rely on bash): PACKAGES = \ module1 \ module2 \ emodule3
TARGETS=clean install all .PHONY: $(TARGETS) default: all FLAGS = $(ifeq $(MAKEFLAGS) "","",-$(MAKEFLAGS)) $(TARGETS): for p in $(PACKAGES) ; do $(MAKE) $(FLAGS) -C $$p $@ || break; done
Thanks!
marcmagransdeabril
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