How can I separate long lines in lines in Verilog

Question

For example, I have one long statement:

$display("input_data: %x, output_data: %x, result: %x", input_data, output_data, result); 

How can I do this in one expression and multiple lines in Verilog?

Answer 1

You need to split the quoted string. Here is one way:

 module tb; initial begin integer input_data = 1; integer output_data = 0; integer result = 55; $display("input_data: %x " , input_data, "output_data: %x " , output_data, "result: %x " , result); end endmodule /* Outputs: input_data: 00000001 output_data: 00000000 result: 00000037 */ 

Answer 2

More generally, you can also use the string concatenation operator:

{"string1", "string2", "string3"}