Is integer overflow in vhdl?

Question

I was wondering if integer overflow is defined in VHDL. I could not find anything in the 2002 specification.

As an example (note, this may not compile, this is just a general example ...):

entity foo is port ( clk : std_logic ); end entity; architecture rtl of foo is signal x : integer range 0 to 2 := 0; begin process (clk) begin if rising_edge(clk) then x <= x + 1; end if; end process; end architecture; 

It is clear that x will go from 0 to 1, and then to 2. It is determined what will happen in the next increment? Is this behavior undefined?

Answer 1

for stand for rtl foo in ghdl:

ghdl -r foo_tb --wave = foo_tb.ghw
. / foo _tb: error: error checking the connection to foo_tb.vhdl: 15
. / foo _tb: error: simulation breakdown

I added a contextual sentence to the Bill foo object and architecture:

 library ieee; use ieee.std_logic_1164.all; entity foo is port ( 

Line 15 is the assignment of signal x:

  x <= x + 1; 

This is a simulation error (occurs at runtime).

From IEEE 1076-1993:

7.2.4 Adding statements

The add operators + and - are predefined for any number type and have their conditional mathematical value.

This means that the result of the “+” operator may be outside the bounds of the subtype x. Note that a function declared to provide overload for "+" cannot indicate a subtype of result. (The return value can be a declared object with a subtype that can determine the range of values ​​or the length of the array).

and 12.6.2 Propagation of signal values

To update a signal during a given simulation cycle, the kernel process first determines the control and effective values ​​of this signal. The kernel process then updates the variable containing the current signal value with the new effective value, as follows:

a) If S is a signal of some type that is not an array type, the effective value of S is used to update the current value of S. It is verified that the effective value of S belongs to subtype S. Error in checking the subtype. Finally, the effective value of S is assigned to a variable representing the current value of the signal.

If the result of the addition does not match the subtype restriction of the target x, it will generate an error. This subtype restriction is provided by the declaration of the object x, which provides an indication of the subtype for an integer (range).

A run-time error terminates the simulation for an implementation compatible with LRM.

Without a standard format for error reporting, ghdl does not provide the current simulation time. This can be found by examining the resulting waveform:

The waveform is completely updated after 20 ns. Next scheduled event:

 library ieee; use ieee.std_logic_1164.all; entity foo_tb is end entity; architecture foo of foo_tb is signal clk: std_logic := '0'; begin DUT: entity work.foo port map ( clk => clk ); CLOCK: process begin wait for 5 ns; clk <= not clk; if now > 30 ns then wait; end if; end process; end architecture; 

would be a clk rising edge of 25 ns.

So this tells us how a limited integer creates an overflow error.

How about an integer without subtype limitation:

 architecture fum of foo is signal x : integer := INTEGER'HIGH - 2; begin process (clk) begin if rising_edge(clk) then x <= x + 1; end if; end process; end architecture; 

We define x as an unlimited integer that sets the default value, where we expect x to overflow.

Standard package explication declares INTEGER "+":

 -- function "+" (anonymous, anonymous: INTEGER) return INTEGER; 

The expected result is outside the range of INTEGER if, as we see, "+" has the usual mathematical value.

However, from an implementation-dependent advertisement in a package standard:

 type integer is range -2147483648 to 2147483647; 

and modeling:

We see that the value of x is wrapped.

Assigning the result of the + operator does not violate the restrictions:

3 Types:

Many possible values ​​for an object of this type can be subject to a condition called a constraint (in the case where the constraint does not impose restrictions, it is also included); a value is considered to satisfy a condition if it satisfies the corresponding condition. A subtype is a type along with a constraint. It is said that a value refers to a subtype of a given type if it belongs to the type and satisfies the constraint; this type is called the base type of the subtype. A type is a subtype of itself; such a subtype is called unconditional (it corresponds to a condition that does not impose restrictions). The main type of type is the type itself.

There is no restriction in our second architecture, but there are no valid values ​​outside the declared range for the INTEGER type. The value instead turned upside down.

The semantics for VHDL were built so as not to require detection here, and this corresponds to mathematical operations on one-dimensional arrays of elements representing binary bits (hardware).

Answer 2

Any worthy simulator will stop there with an error message indicating exactly the add that has overflowed. (Xilinx Isim is only a decent simulator, if you did not forget to turn on the checks, the last time I watched)

Spooky, if you've done too much C programming over the years!

The synthesis will do everything that saves equipment (in this case, without exits, optimize X and the process completely!), So it is best to catch such an error in the simulation.

Answer 3

Integer overflow (and underflow) is the behavior defined by the implementation in VHDL. I cannot quote the spec at the moment, but if you read carefully, you will see that almost everything about integer ranges is determined by the implementation outside the minimum supported range ( -2**31 to 2**31 ).

Most VHDL implementations on 32-bit machines actually behave as if they were 32-bit integers (for example, how whole numbers of machines behave on these platforms), and 64-bit implementations usually have 64-bit integers but you cannot count on it.

In your specific example, if you use an integer subtype with a range, if you try to assign a value outside this range, it will be an error and will generate a statement at runtime. (Synthesizers, on the other hand, will do whatever weird thing they want - they usually overflow, as if it were an integer of 2 additions).