Can I use custom types in a port declaration?

Question

I am preparing for the exam, having passed a few old ones. One of the questions:

Write the synthesized behavioral code VHDL that implements synchronous FSM in Figure FSM has one input, called a query, which has an enumeration type with values ​​(r1, r2, r3) ...

This makes me write this code:

entity fsm is port ( clk : in std_logic; request : in my_enum_type ); end fsm; 

And somewhere there is:

 type my_enum_type is (r1, r2, r3); 

somewhere (I tried right before the port declaration and right after the architecture declaration).

But I can't get this to work. Can I have custom types as inputs or outputs?

Answer 1

Yes, you can, and I consider this the best practice — this is the smallest work, the best understanding, ease of maintenance and the cleanest design.

The trick is to declare types that are common to all of your constructs in a package (usually I call it "Common" :-) and add use work.Common.all before declaring an AND object for each client of that object. Of course, more specialized components may have corresponding names!

For example:

 package Common is -- untested... type my_enum_type is (r1, r2, r3); -- (optional) useful tools function to_slv (e : my_enum_type) return std_logic_vector; function to_enum (s : std_logic_vector(my_enum'length downto 0)) return my_enum_type; end Common; package body Common is -- subprogram bodies here end Common; 

Now, when you add a value to the enumeration, you ONLY change the "Common" and rebuild the design, while those who adhere to the usual recommendations are still trying to identify each port and signal where they need to increase the range of their "std_logic_vector" by 1 .

It also works well for bus interfaces, where recording in each direction hides all individual signals and acknowledgment signals.

You will have to deal with brain tools, such as the Xilinx automated test bench generator, which will help translate ALL of your port types - integer or logical, as well as custom - into std_logic (_vector) and then not compiled. Just translate them back.

You can still make the case where at the highest level, all external FPGA pins should still be based on std_logic. And if you ever need to model the post-synthesis version of your design, you will either need to live with the std_logic_vector ports, or add a simple wrapper to convert from one form to another.