Why are CISC processors more pipelined? In what sense are some instructions “more complex” than others?

Question

According to the "Architecture and Organization of Computers" by Miles Murdoch and Vincent Heuring,

CISC instructions are not well suited for pipelined architecture. For the conveyor to work effectively, each instruction must be similar to other instructions, at least in terms of the relative complexity of the instruction.

Why is this true? What is meant by the complexity of the instruction; Do not all instructions take one clock cycle to begin execution? If the instruction reads or writes to memory, then it will take more time, but RISC processors also read or write to memory (of course)?

Answer 1

The “complexity” of instructions is related to how much their size and format can vary. Take the x86 IA32 (Intel 32-bit) architecture, such as CISC. The size of instructions can vary from 1 to 15 bytes, and their format also varies greatly (format is the number of bits used for each field where these bits are located, etc.).

This means that you only find out when you finish retrieving the instruction as soon as you start decoding it. Some instructions will receive only one cycle, others more, and this complicates the pipeline process.

On the other hand, all ARM instructions (RISC architecture) have exactly 4 bytes. Therefore, having received 4 bytes, you know that you can send these bytes for the decoding phase of the pipeline, and you can immediately start fetching the next instruction.

Answer 2

What is meant by CISC architecture, there are usually instructions that are relatively longer than RISC. Therefore, planning is more difficult. At CISC, simple instructions are often found, and more complex instructions take longer. Thus, there are things in the pipeline called hazards that can cause problems for smooth conveyor processing. X86 floating point instructions will be longer than loading or saving x86, for example.