They do not necessarily match your status at the first point in the ISR: interrupts are asynchronous and therefore must somehow "interrupt" the operation of the main processor (s).
For example, let's look at this address-decorated MIPS code that does nothing useful:
4000. add $1, $2, $3 4004. sw $ra, 0($sp) 4008. jal subr # function call, sets $ra to 4012 and jumps to 4024 4012. lw $ra, 0($sp) 4016. jr $ra 4020. 4024. subr: sub $2, $1, $3 4028. jr $ra
This code can be transmitted from the main processor: arithmetic operations (lines 1, 7) are performed by the arithmetic device, memory access (lines 2, 4) by the memory controller and jumps (lines 3, 5, 8) are also performed by the main processor. (The actual jal address is set during the binding of the object file.)
This is for function calls. At any time, it is determined where the code is right now and what code is executed at the next moment in time (that is, when the program counter increases: PC + = 4).
Now comes the moment when your functions do something complicated, but you still want the software to respond to a keystroke. Then the so-called coprocessor comes into play. This coprocessor waits until an event occurs (for example, a key stroke on the keyboard), and then calls the interrupt handler. This is a block of code located at a specific address in memory.
Think of the processor in the calculation above, but in the meantime you want to save the number of keystrokes at the keys address. Then you write a program starting with the address 0x80000180 (this is defined as the address of the exeption handler in MIPS):
lw $at, keys addi $at, $at, 1 sw $at, keys eret
Now what happens when you press a key?
- The coprocessor learns about a key press.
- The current PC of the main processor is saved
- The main processor PC is set to 0x80000180, an interrupt code is executed
- In
eret PC is installed on the PC of the main processor before the interruption occurred. - The main program execution continues.
There is a transition from normal execution to handling interrupts between steps 2 and 3 and vice versa from 4 to 5.
Note. I simplified this a lot, but it should be clear how interrupts differ from function calls and how hardware should have additional capabilities for handling interrupts.