Stage 2 MemAttr Long ARM Descriptor PTE Request

Question

For the translation in step 2 there is a field with lower attributes called MemAttr [3: 0] An exhaustive listing of all possible values ​​gives the following table

/* All Possible Values of MemAttr for Stage 2 */ /* * 0000 Region is Strongly Ordered * 0001 Device Memory [ONC by Default] * 0010 XXXXX * 0011 XXXXX * 0100 XXXXX * 0101 Normal Memory O NC, I NC * 0110 Normal Memory O NC, I WT C * 0111 Normal Memory O NC, I WB C * 0100 XXXXX * 1001 Normal Memory O WT C, I NC * 1010 Normal Memory O WT C, I WT C * 1011 Normal Memory O WT C, I WB C * 1100 XXXXX * 1101 Normal Memory O WB C, I NC * 1110 Normal Memory O WB C, I WT C * 1111 Normal Memory O WB C, I WB C */ 

O - External I - Internal WB-WriteBack WT-WriteThrough NC - Non Cacheable C - Cacheable.

Now I wonder what normal memory is assigned to the guest, what should be the values ​​that I should put in mem attr. I'm just looking for WriteBack Cacheable.

Answer 1

Normal write-back cached is what you want for any general purpose RAM mappings. If you are not doing something special, you want it for internal and external caches.