Using two USART systems operating at 115200 baud on the STM32F2, one for communication with the radio module and one for serial communication with the PC. The clock frequency is 120 MHz.
When receiving data from both USARTs, overflow errors on one USART or the other may occur at the same time. When doing some quick envelope calculations, there should be enough time to handle both, because interrupts just copy the bytes into the circular buffer.
Both in theory and in measurement, the interrupt code for pushing a byte into the buffer should / should be executed in the order of 2-4 ฮผs, at 115200 baud we have about 70% for processing each char.
Why do we see random ORE on one or the other USART?
Update - additional information:
- There are currently no other ISRs in our code.
- We start Keil RTX with a systick interrupt configured to start every 10 ms.
- We will not disable interrupts at this time.
- According to this book (Cortex-M Processor Designer's Guide), latency interpolation is about 12 cycles (not very fatal)
Given all of the above 70us, at least 10 times in the time that we do to clear interrupts, so I'm not so sure that it is so easy to explain. Should I conclude that there must be some other factor that I am experiencing?
MDK-ARM - version 4.70
The systick interrupt is used by RTOS, so from time to time another ISR does not need 2-3 ยตs for each byte.
interrupt embedded serial-port stm32
Jonathan moreton
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