As Jeffrey Bosbum and Hans Passant noted their comments, the reason is simplicity. More specifically, the simplicity of the hardware.
LD r,r' instructions copy the contents of the source register ( r' ) to the destination register ( r ). The LD r,r' operators follow this form:
------------------------------- BIT | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ------------------------------- OPCODE | 0 | 1 | r | r' | -------------------------------
The destination and source registers can take the following values:
----------- | BIT | REG | ----------- | 111 | A | ----------- | 000 | B | ----------- | 001 | C | ----------- | 010 | D | ----------- | 011 | E | ----------- | 100 | H | ----------- | 101 | L | -----------
To implement these instructions on hardware, we just need a multiplexer that accepts bits 0-2 to select the source register and another multiplexer that accepts bits 3-5 to select the destination register.
If you want to check if bits 0-2 and bits 3-5 indicate the same register, you will have to add more logic to the CPU. And, as we all know, ressources were more limited at 80: P
Please note that loading instructions such as LD A,A , LD B,B , LD C,C , LD D,D , LD E,E , LD H,H and LD L,L behave like NOP . However, AND A and OR A DO NOT behave like NOP , since they affect the flag case, and their execution can change the internal state of the machine.
GabrielOshiro
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