RISC means “set of abbreviated instructions” (usually the LOAD register, the STORE register, the ADD register, the CMP register, the conditional branch condition + several others).
The concept and experience is that complex instructions often do not provide a useful effect that cannot be achieved through simpler sequences of commands, especially if the additional logic that will be used to implement such complex instructions is instead invested in creating simple RISC instructions faster.
PUSH and POP are basically simple combinations of STORE / LOAD indirect, and ADD is constant in register. Thus, if one allocates a register for the stack pointer, PUSH and POP are easily simulated, and a fast pipeline machine can probably execute PUSH and POP as fast as the corresponding RISC instructions. Therefore, most of them PUSH and POP should be CISC instructions; they really don't buy you much.
Life becomes more interesting if you consider CALL (== PUSH PC + JMP) and RET (POP PC). They are also easily modeled on the right RISC architecture. However, the POP PC carries a piping bubble because the processor cannot predict where the new PC will be, and therefore cannot prefetch. Since memory is “far in time”, it can be a major performance inhibitor in code with many subroutine calls.
Here one kind wants to go CISC. What you really want is some way to predict what a PC returns. Many modern processors do this by storing the shadow call stack in the hardware. Each CALL pushes a PC onto the memory stack as well as into the shadow stack; each RET returns the value of the PC from the memory stack, but predicts the flow of the instruction stream using the upper element of the shadow stack, which has almost zero access to (and, of course, the shadow stack pops up). Thus, the flow of commands is not interrupted, and therefore the CISC machine benefits from performance.
(Interestingly, if a RISC machine with a large number of registers, compiled leaf function functions always use a register to store a reverse PC, it may not be as efficient as a shadow stack. Sun Sparc does this using its register window).
This suggests that RISC and CISC simplify the trade-off between projects. What you want is simple if the more complexities don't really buy you. For example, IEEE floating point in hardware is much faster than any simulation using RISC instructions.
As a result, most modern machines are not neatly RISC or CISC. Performance profiling is selected.