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How to remove I / O port declarations using regexp in verilog mode

I am trying to create an instance of the abc_d module, and I do not want all its ports to be declared as I / O ports in the top abc module. I want to exclude ex_out_port for declaration as output port.

 module abc(/*AUTOARG*/); /*AUTOINPUT*/ /*AUTOOUTPUT*/ /*AUTOWIRE*/ abc_d u_abc_d(/*AUTOINST*/); endmodule //Localvariables: //verilog-auto-output-ignore-regexp:("ex_out_port") //END:

expected code:

  module abc (/*AUTOARG*/ /Inputs input port1; input port2; /Outputs output port3; output port4; /*AUTOWIRE*/ wire ex_out_port; //Instance abc_d u_abc_d(/*AUTOINST*/ .port1 (port1), .port2 (port2), .port3 (port3), .port4 (port4), .ex_out_port (ex_out_port)): endmodule

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1 answer

Your verilog-auto-output-ignore-regexp bit off. It works after dropping parentheses around "ex_out_port"

 //verilog-auto-output-ignore-regexp: "ex_out_port"

I was unable to find gnore-regexp code examples in the documentation or FAQ. I found one example in the forum on the veriloop website (verilog-mode owners): https://www.veripool.org/boards/15/topics/1635-Verilog-mode-Scope-for-AUTO_LISP-

FYI: If you are strictly following Verilog-1995 syntax or not using an outdated version of verilog-mode, you might consider changing it:

 module abc(/*AUTOARG*/); /*AUTOINPUT*/ /*AUTOOUTPUT*/ /*AUTOWIRE*/

To the ANSI style header, which is supported with Verilog-2001:

 module abc( /*AUTOINPUT*/ /*AUTOOUTPUT*/ ); /*AUTOWIRE*/

This is functionally and behaviorally the same with fewer lines of generated code.

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