My preference is that your testbed has one module (or a small number of modules) that contains all your probes, but no other functions. All other modules of your test bench that require probes are then connected to this "probe module". Use SystemVerilog interfaces, preferring raw wires, if this is an option for you. This circumvents your problem, since no observer will require global hierarchies, and your test bench as a whole will be much easier to maintain. See the Law of Demeter .
Alternatively ... (but this puts the hierarchy in your instances ...)
module watcher(sig, bar); input sig; input bar; ... endmodule watcher w1(`HIER1.sig, `HIER1.foo.bar); // instantiation watcher w2(`HIER2.sig, `HIER2.foo.bar); // second instantiation, except with a different hierarchy
Subsequently, you can also:
`define WATCHER_INST(NAME, HIER) watcher NAME(HIER.sig, HIER.foo.sig) `WATCHER_INST(w1, `HIER1); `WATCHER_INST(w2, `HIER2);
DMC
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