MIPS floating point: swc1 vs. ss

Question

I do some work with the MIPS assembly, and I constantly come across these four floating point aliases: ls , ld , ss , sd . I found the documentation on the Internet and realized that there are four “actual” instructions that seem to do the same thing: lwc1 , ldc1 , swc1 and sdc1 .

My only question is: what's the difference? As far as I can tell, both sets of instructions do the same. Perhaps pseudo-exist only because they are easier to read?

Thanks in advance for your understanding.

Answer 1

My only question is: what's the difference? As far as I can tell, both sets of instructions do the same.

Yes you are right. The only difference that can occur is when a pseudo-instruction is translated into more than one "real" instruction.

Is it possible that pseudostations exist only because they are easier to read?

Again, yes. This is why they exist. They give the illusion of a more expressive set of instructions. Quote Organization and design of computers / Patterson and Hennessy :

... the assembler can also process common variants of machine language instructions, as if they were instructions on their own. Hardware must not follow these instructions; however, their appearance in assembly language simplifies translation and programming ....

Given your example, more "understandable":

 ls $f2, 24(t1) # Load Single contained in 24(t1) to $f2 

than

 lwc1 $f2, 24(t1) # Load Word into Coprocessor 1 from 24(t1) to $f2 

and also you can better understand:

 move $7, $18 # move contents of $18 to $7 

than

 add $7, $18, $0 

For me, it just helps the mnemonics get a clearer code.

Answer 2

I actually think

 LWC1 is Load Word to Co-processor 1 LDC1 is Load Double Word to Co-processor 1 

etc...

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Guess what I hit on the Patent page, trying to remember them.

US Pat. No. 5,555,384 - Rescheduling of conflicting issued instructions by delaying one conflicting instruction to the same pipeline stage as the third conflict-free instruction

There are two types of boot instructions implemented by FPC 20:
LWC1 (Word loading coprocessor 1 shown in FIG. 4) and
LDC1 (Coprocessor 1 for loading two words, shown in Fig. 8).

LWC1 loads a 32-bit word from the memory subsystem into shared FPC registers.
LDC1 loads a 64-bit double word from the memory subsystem into shared FPC registers.

which confirms this.
(by the way, do not bother looking for the numbers indicated here if you do not have access to the site).