Skip makingfile dependencies for specific purposes (e.g. `clean`)

Question

I have several projects in C and C ++ that follow the basic structure that I have been using for some time. My source files are in src/*.c , intermediate files are in obj/*.[do] and the actual executable is in the top-level directory.

My makefiles follow something like this pattern:

 # The final executable TARGET := something # Source files (without src/) INPUTS := foo.c bar.c baz.c # OBJECTS will contain: obj/foo.o obj/bar.o obj/baz.o OBJECTS := $(INPUTS:%.cpp=obj/%.o) # DEPFILES will contain: obj/foo.d obj/bar.d obj/baz.d DEPFILES := $(OBJECTS:%.o=%.d) all: $(TARGET) obj/%.o: src/%.cpp $(CC) $(CFLAGS) -c -o $@ $< obj/%.d: src/%.cpp $(CC) $(CFLAGS) -M -MF $@ -MT $(@:%.d=%.o) $< $(TARGET): $(OBJECTS) $(LD) $(LDFLAGS) -o $@ $(OBJECTS) .PHONY: clean clean: -rm -f $(OBJECTS) $(DEPFILES) $(RPOFILES) $(TARGET) -include $(DEPFILES) 

Now I am at the point where I am packaging this for the Debian system. I use debuild to create a Debian source package and pbuilder to create a binary package. The debuild step should only perform clean target, but even this leads to the creation and inclusion of dependency files.

In short, my question really is: Can I somehow prevent make from generating dependencies when all I want to do is run clean target?

Answer 1

The solution is easy, not -include generated files under cleanup:

 ifneq ($(MAKECMDGOALS),clean) -include $(DEPFILES) endif