Place and route FPGA

Question

For FPGAS programming, is it possible to write your own place and routing procedures? [The point is not that mine would be better; the point is, do I have the freedom to do this] - or does the stage and stage stage give out in undocumented bitfiles, which forces me to use my own tools?

Thanks!

Answer 1

This has been discussed in the past at comp.arch.fpga. The conclusion, as a rule, is that if you do not want to engage in action from FPGA companies, you probably do not want to do something like that. bit formats are FPGA companies' carefully guarded secrets, and you may have to understand the file format in order to do what you want to do. This implies that you will need to reverse engineer the format and that (if you make your tool publicly available in any way), you will receive a lawsuit in a short time.

I will add that there are probably intermediate files, and you probably won’t read or write the bit of the file itself to do what you want, but these intermediate files are also not documented. Read the EULA for your FPGA synthesis tool (such as Xilinx ISE) - any reverse engineering is strictly prohibited. It seems that the only way we will ever have open source alternatives in this space is to create an open source FPGA architecture.

Answer 2

I agree with annccodeal, but with a bit of effort, on Xilinx, there may be several ways to do this. The XDL file format allows (or allows) explicit location and routing. In addition, the FPGA Editor script should be possible to implement custom routing.

As for placement, there is a rich infrastructure for limiting the technological mapping of logic to primitives and controlling the placement of these primitives. For example, LUT_MAP constraints can control technology mapping, and LOC and RLOC constraints can determine placement. In practice, this allows an experienced designer to distinguish control over how the design is implemented, without requiring them to duplicate software development for people through the ages in order to generate a bit stream directly.

You can also find interesting current state-of-the-art FPGA CAD research software such as VPR . In my opinion, they have to keep up with the supplier’s own tools, which must cope with modern heterogeneous FPGAs with 6-LUT splittable, DSP blocks, etc.

Happy hack.