Why do I need to update VHDL components before creating them in other architectures?

Question

I scratch my head from the first class of VHDL and decided to post my question here.

Given that I have an declared object (as well as its architecture) and you want to create it in a different architecture, why does it seem to me that I, apparently, should redefine the "object" (component) inside this containing architecture before creating his

Isn't the compiler smart enough to match an instance of its architecture only by its name? Where is component declaration needed?

Answer 1

You can directly instantiate the component if you want:

MyInstantiatedEntity : entity work.MyEntity_E generic map ( config => whatever) port map ( clk => signal1, clk_vid => signal2, ... 

Creating a component declaration gives you the added opportunity to change what is tied to instantiation using a configuration specification or similar.

Answer 2

Back when my VHDL assignments returned when I was at school, I needed to have all our code in one file, so I don’t remember if you could write one file for each module and how it was done.

In this case, you will need to declare an object that you would use when defining behavior, if you would use it in the same way you would define prototypes, structures, classes, and something else in C or C ++. The difference here is that you don’t have the luxury of defining the header files for this “re-declaration” in VHDL (at least I don’t think there is an equivalent). Therefore, it seems quite reasonable to me that I should do this. Note that VHDL came out when C was very common, and the compilers were not "smart enough" as they are today.

The VHDL guru may have a definitive answer for this, but as I understand it.