Is the make file basically the same as the batch file?

Question

I know everything about batch files and did them before, but I don’t understand what a make file is. It looks like a batch file. What are the similarities and differences?

Answer 1

No. There are special rules in the makefile that determine how the files depend on each other. It is not necessarily executed in the order in which it is written.

A batch file is a sequence of commands and control statements.

Makefiles often contain the same things as batch files, but batch files do not have a direct way to specify dependencies or provide the intended method of processing one kind of file in another.

Answer 2

Similarly, yes, except for dependencies, topological sorting, macro processing and expert system

If you do nothing but shell commands in the Makefile, then this is actually very similar to the “batch files” directory, and it executes each one when the associated target is specified.

However, it is more typical to specify a dependency graph in a makefile, in which case make does a topological sort . all dependencies to intelligently build everything only once and in the correct order, starting with the earliest prerequisites.

And to be complete, I have to add that make is also a macro processor. It focuses on software creation systems; therefore, it provides processing of symbolic elements in its problem area, such as source and target names.

Now make is not a specially specialized expert system, ¹ but it does more than just batch shell code, and technically it meets the definition of an expert system.

Make contains an output mechanism . All versions of make have suffix rules . Some versions also implement template rules . In combination with your specification (more rules that usually define a software application), the result is an expert system that will decide what to compile, link, acquire on eBay , regardless of whether it depends on the data and commands you provided.

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^{1. Instead, it is an easy-to-use expert system. Skynet probably won't appear from a random typo in a complex Makefile.}

Answer 3

To draw a pretty abstract spin on it:

• Batch files are written in an imperative language.
• Make files are written in a declarative language for processing files (which is intended and usually used to control assembly).

Answer 4

Makefiles lists the commands that are executed, but they are structured differently than a list of consecutive commands. Instead, they have goals and teams to “make” them. make then checks the listed dependencies and sees which goals need to be updated in order to do what you said. There are many implicit rules (assuming the * .c file already knows how to compile it into * .o and even create an executable!) And standard variables (like CFLAGS) so that you can take advantage of this. And, contrary to the man page, you can use these implicit rules without a Makefile .

The easiest way to think about what makefile says is how to make "A" set to "B", and then you say you want to do what you want (like make all ), and not how to do it. It defines the individual steps.

• GNU Link

Answer 5

Very interesting question. With a shell script or batch file, you provide the computer with a list of instructions that must be followed in order. It starts from above, works until it reaches the end, and then stops. Well, there may be function definitions, loops, and gotos that change the exact order in which events occur, but mostly talk about the progress in the file, linear.

Makefiles, on the other hand, provide a series of instructions on how to do certain things from some other things. When you invoke make , you tell him what you want and analyze the instructions that he has and decides which one he must execute in order to make your specified goal. As a result, what happens when the make file is called depends not only on the contents of the file itself, but also on what you asked to do and on what state your files are at this point.

Two different approaches for performing two different actions.

Answer 6

Not at all. They are similar in the sense that all programming languages ​​are similar (especially since they are both scripts), but they have different goals.

The purpose of make files is to describe how to create a project. This usually means creating rules (in a special language) that say things like:

• whenever you see a file that ends with .c, run the gcc program to compile it into the .o object file.
• whenever you have a group of .o, associate them with .exe.

Of course, this is a simplified description.

The main advantage of using make (the "interpreter" for the makefile language) is that you get syntax that is designed for such things. For example, make typically performs actions such as checking whether a file has changed so that you do not compile a file that does not have any changes.

Answer 7

Makefiles are data for the Make program. Think of them as what the old guys did before they got the XML :)