Temporary restrictions

Question

I am developing a ULPI interface for communication with a USB chip.
But I ran into some problems regarding time limits.

Data is displayed on the leading edge of the watch and selected on the falling edge.

I can see (using Post-Route) that there is about 6 ns of the “best possible delay” from the moment the time increases until the data is released.

If I need a little delay, should I rewrite my code and, for example, hold my watch until the leading edge rises with the data?

I know that the above solution is probably not very good, since it will be both an fpga device and a route dependent one ... But what other options exist?

Answer 1

Is your data register registered in the I / O register? Restriction in UCF: INST "some_ff" IOB = TRUE; Or you can use the -pr b map option, which will package the inputs and outputs ([b] oth) into io registers.

This has 2 effects:

• Blocks synchronization between IO pin and first / last pin D / Q FF (build to build consistency)
• Maximizes the performance of the output clock (you cannot bring Q closer to the output pin).

Edit: The above recommendation applies to Xilinx tooling objectives. Other providers probably have similar architectures, but the arguments / controls needed to invoke the option are different.

Answer 2

Assuming Xilinx device:

Consult the FPGA editor for where triggers are located. Sometimes, if they are derived from the top-level block, the tools will not pack them in the IOB, even if the UCF and parameters are set so that they should be.

As a workaround, adding an extra layer of triggers at the top level can help. Or you could create an instance of the ODDR2 block to cause a problem, and just connect two data inputs to the same internal signal.