Why is memory alignment required?

Question

Possible duplicate:
Memory Alignment Assignment

I read several articles about the network on memory alignment and realized that from a correctly aligned memory (with two-row alignment) we can quickly receive data at a time.

But if we have memory as a separate piece of equipment, then, given the address, why can not we read 2 bytes directly from this position. eg:

I thought about it. I think that if the memory has odd banks, then the theory is applicable.

What am I missing?

Answer 1

Your photos describe how we (people) visualize computer memory.

In fact, think of memory as a huge matrix of bits. Each column of the matrix has a “reader” that can read / write any bit from this column. Each row of the matrix has a “selector” that can select a specific bit that the reader will read / write.

Therefore, this reader can immediately read the entire selected row of the matrix. The length of this row (the number of columns in the matrix) determines how much data can be read at once. For example, if you have 64 columns, your memory controller can read 8 bytes at once (usually this can do more than that).

As long as you keep your data aligned, you will need less of these memory accesses. Even if you need to read only two bits, but they are located on different lines, you will need two memory accesses instead of one.

In addition, there is a whole aspect of writing, which is another problem.

Just as you can read an entire line, you can also write an entire line. If your data is not aligned when you write something that is not a complete line, you will need to perform read-modify-write (read the old contents of the line, change the corresponding part and write new content).

Answer 2

Data from memory is usually delivered to the processor via a set of wires that matches the width of the bus. For example, if the bus is 32 bits wide, 32 data wires (along with other wires for control signals) are sent to the processor from the bus.

Inside the processor, various wires and switches deliver this data to where it is needed. If you read 32 aligned bits into a register, wires can deliver data directly to the register (or other storage location).

If you read 8 or 16 aligned bits in a register, wires can deliver data the same way, and the rest of the bits in the register are zero.

If you read 8 or 16 unbound bits in a register, wires cannot transfer data directly. Instead, the bits should be shifted: they must go through a different set of wires so that they can be "moved" to align the wires in the register.

On some processors, designers put extra wires and switches to do this. This can be very expensive in terms of the amount of silicon that is required. You need a lot of extra wires and switches so that you can move any possible unbalanced bytes to the right places. Since it is so expensive, on some processors there is no complete switch that can immediately make all the changes. Instead, the switch can only move bits bytes or so on each CPU cycle, and several cycles require several cycles. Some processors do not have wires for this, so all loads and storage should be aligned.

Answer 3

In the first case (a separate part of the hardware), if you need to read 2 bytes, the processor will have to issue two read cycles, this is because the memory is addressed by a byte, and each byte is provided with a unique address.

Organizing memory as banks helps the processor get more data into the registers in a single read cycle. This method helps to reduce read cycles, which is a very slow process compared to processor bandwidth. Thus, for one reading cycle, you can read more data.