VHDL Structural vs Behavioral

Question

This is a question for those who are well versed in VHDL. I am new, but so far I have created VHDL using a behavioral description. It’s much easier for me to think, since it is like writing software. I know that a possible fall is that the behavioral is "executed" sequentially, and the structural execution is simultaneously within the component / development process.

So I'm just wondering if I have an architecture that uses a process, like an 8-bit shift register (SISO) and I want to create 4 instances of these (4x8 bit shift registers), I would create a component and 4 process instances ?

Or would I generate 4 processes (run parallel to each other) and just call each process under a different name?

It’s also just a general question to get consensus on which good practices people use there, which one do you prefer: structural or behavioral? When is the right time to choose one after another? I suggest that they may be useful with "faster" execution using components that allow internal concurrency compared to sequential execution of processes. Of course, it seems to me that you can reduce development time with behavioral projects ..

Thanks! ~ Doddy

Answer 1

For my money, the role of structural HDL is currently limited to linking proven working behavioral blocks (or connecting untested to their testbeds!). I agree with you regarding the superiority of behavioral VHDL in terms of creating and testing design time.

I also agree that writing a behavioral process is somewhat similar to writing software (over the screams of some that it’s not)

HOWEVER

Do not fall into the trap of equating behavioral sequence or slow!

Given your shift register, say

type reg_type is array(7 downto 0) of bit; signal s_in, s_out : bit; process(clk) is variable reg : reg_type; begin if rising_edge(clk) then s_out <= reg(7); reg := reg(6 downto 0) & s_in; end if; end; 

I can trivially parallelize it as follows:

 signal p_in, p_out : array(1 to 4) of bit; process(clk) is variable reg : array(1 to 4) of reg_type; begin if rising_edge(clk) then for i in reg'range loop p_out(i) <= reg(i)(7); reg(i) := reg(i)(6 downto 0) & p_in(i); end loop; end if; end; 

(And yes, there are simpler ways to write this!) It’s important to note that the loop no longer starts: it just generates more hardware (in the software it is fully deployed). Each iteration is completely independent of the others; if they were not, everything would be more complicated.

Do not worry about academic differences between structural and behavioral.

Beware of the difference between scheduling the assignment of signals and scheduling the assignment of variables in the process (find out which delta loops and delayed assignment are one of the key differences from software, and arises because the software only has variables, not VHDL signals). will explain why I implemented the pipeline upside down here (first output) - because I used the variable.

Worry about why so many people are teaching an idiotic 2-processing computer when the 1-process SM is simpler and safer.

Find and understand Mike Trezeller’s pages about single-process models (I hope they’re still online)