An arithmetic shift acts like a logical shift, regardless of the signed variable

Question

I have a register declared like this:

logic signed [15:0][2:0][15:0] registers; 

When I put in the array 2 the number of compliments and arithmetically change their number, it instead logically shifts:

 registers[0][0] = 16'b1000000000000000; registers[0][0] = registers[0][0]>>>2; 

Apparently, the system will be a logical shift instead of an arithmetic shift if the number is not signed. However, as you can clearly see, the "registers" are definitely signed.

Does anyone know what I'm missing here?

Thanks!

Answer 1

With Verilog, as soon as you take the select part, the result will be unsigned . Use the $signed system task to select a part to make it signed.

 res = $signed(registers[0][0]) >>> 2;