Verilog: value (s) do not match array range, model mismatch

Question

The following code synthesizes and simulates correctly, as far as I can tell, but XST still gives the following warning : value(s) does not match array range, simulation mismatch. Is there something I am missing?

Tool Used: Xilinx ISE Project Navigator (Synthesizer: XST) FPGA: SPARTAN 3E

 module error_example( input [47:0] data, input [2:0] sel, output [5:0] data_out ); assign data_out = data[sel*6 +: 6]; endmodule 

WARNING:Xst:790 - "error_example.v" line 8: Index value(s) does not match array range, simulation mismatch.

As I said, this works, and I did the math:

sel can have values ​​from 0 to 7,

if sel is 0, then data_out = data[5:0] ...

if sel is 7, then data_out = data[47:42]

Should I do something different here? Is this a bug in XST?

Answer 1

I created an example on EDAplayground that runs without warning.

I would usually not use the width with parameter , and if possible, you can accept the definition of reg.

Try:

• parameter data = 48'h123456789ABC;
• parameter [47:0] data = 48'h123456789ABC;

I don’t think I used the parameters in this way before, but declaring the reg constant implies the same logic that could have avoided the warning.

• reg [47:0] data = 48'h123456789ABC;

NB: It's good to use uppercase for constants ( parameter , localparam ).

Alternatively convert to case statement:

 always @* begin case (sel) 3'd0: data_out = 6'dx; 3'd1: data_out = 6'dx; // ... default : data_out = 6'd0; endcase end