The relationship between the number of logical cells on the FPGA and performance

Hey, I have a question about FPGA. If you look at the current xilinx product line, in particular on the 7 series, there is a huge price gap between each of the models. I don’t understand if I can buy Artix-7 with ~ 200k logic cells for $ 300, while Virtex-7 logic cells with ~ 2000k cost more than $ 20,000. Can I just buy 10 Artix-7 and get the same performance? In addition, performance is linearly related to the number of logical cells, and if not, how are they connected? Is there any advantage to having more logical cells on the core? I am sure it depends on what you are doing, but since my interest in the case, although theoretical, lies in cryptographic applications, my question relates specifically to implementations of MD5, SHA-0/1/2/3 and similar encryption algorithms .

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FPGA does not have "performance" like a processor. This is just a bunch of logical elements (LEs) that you can use. If the high-end part has 2MLE and the younger part has 200kLE, but you only need 20kLE for your processing core, it does not very much depend on which one you use, all other things being equal. Of course, if you have a problem that can be easily parallelized, you can turn these additional LEs into extra performance by building more processor cores. But you have to do it.

Now everything else is not always the same, because FPGAs are much more than just the number of logical cells. I can’t talk about Xilinx components (I work for another major FPGA vendor), but usually upscale families will have things like very high speed transceivers that aren’t in the middle and younger families. In addition, sometimes they have different combinations of internal memory, DSP, etc.

So can you use a bunch of small FPGAs instead of a large one? Remember that an FPGA will only have about 1000-2000 IO, while there will be more than 100K internal wires between the corresponding parts of the top. Thus, you will not only need to create a rather complex board, you may find yourself IO-limited in receiving signals from one chip to another.

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