If approved, causing the output latch in Verilog?

Question

I write Verilog code for synthesis algorithm, I'm a little confused as to which cases can cause the latch. Below is one such section of the code, although it works fine in simulation, I am worried that it could cause problems with the equipment.

always@ (b1 or b2) ..... // b1_map,b2_map,m1_map & m2_map are derived from combinational functions using b1 & b2 ..... if(b1_map<=20 && m2_map<=20 && b1_map>=0 && m2_map>=0) begin accumulator1[b1_map][m2_map]= accumulator1[b1_map][m2_map] + 1; end if(b2_map<=20 && m2_map<=20 && b2_map>=0 && m2_map>=0) begin accumulator2[b2_map][m2_map]= accumulator2[b2_map][m2_map] + 1; end //accumulator1 & accumulator2 are 2d registers mapped like 2d arrays 

So in this case I want the data to be displayed only if they are listed in the specified limits. Will there be a latch because there is no “other” scenario? I did not add an else statement because I do not want to do anything with this data if it is not within.

Answer 1

If you correctly write their statements if, you'll be fine. Latches are generated when there is a path through the if statement, which does not update one or more outlets. A code similar to the following, generates latch:

 always @* begin if (a) begin b <= c & d; e <= f; end else begin b <= c | d; end end 

Please note that e is assigned only when a true? This requires the correct implementation of a latch.

Another possibility that will generate a latch is when the sensitivity list does not contain the signal used in the code.

 always @(a) begin if (a) begin b <= c & d; end else begin b <= c | d; end end 

This code will generate a latch on the c and d or b, because it allows only update when you change b.

Answer 2

You misunderstood your problem (and you should not have accepted the answer) - the question is fundamentally not related to “latches”. Your code does not make sense (for synthesis). Quartus knows it, and it basically tells you rewrite your code.

Do you have a combinatorial unit, which increases the number (once) when a change in signal. Two problems: (1) it is certainly not what you want in real (2) the number must remain constant and do not increase when b1 and b2 are not changed. Isue second - the one about which Quartus reports - your circuit needs some memory, which it reports as "latch". This is not smart enough to tell about the first problem that is a real problem.

Try to draw a diagram as a framework with real equipment. What does the change in the b1 and b2 'actually mean? How are you going to maintain the value of the batteries when b1 and b2 are not changed? Driving is not impossible, but it goes beyond the question of SO.

Make synchronization circuit, starting at the edge of the clock, only the clock (and, possibly, reset) in the sensitivity list, and just keep the inside of the same. There is nothing wrong with your statement, if , since you actually want the battery remained intact if anything interesting happens on the b1 / b2.

Answer 3

Estimated latch may be obtained from the partial or incomplete sensitivity list of appointments.

Sensitivity lists for combinatorial units usually must be written with the help of always @* . This allows you to avoid errors when updating the code. Combinatorial blocks (those that do not include sensitivity to the edge) will one day be synthesized to be performed way always @* . In particular, naming signals add more work and are likely to lead to RTL errors for the gate level (postsynthesis).

Incomplete tasks, which imply that the value should be carried out, withdraw the latch. Latches are not inherently bad, but require careful consideration. The method thus derived eliminates the fullness and control of the thoughts that you would otherwise have over it. This can lead to complex sentences. Since the latch is sensitive to the level of, and is not sensitive to the edge. Ideally you want to latch was opened for the first few hours of the clock cycle, so that it is closed when the data will be read from it. The deduced lock removed this control.

Finally, if the instructions with the else, the default case castanets, which establishes a reasonable value (0), can help to avoid these accidental catches.