What is the practical difference between implementing FOR-LOOP and FOR-GENERATE? When is it better to use one over the other?

Question

Suppose I need to check different bits for std_logic_vector. would it be better to implement one process, which for loops for each bit or to create "n" processes using for-generate, on which each process checks one bit?

FOR-LOOP

my_process: process(clk, reset) begin if rising_edge (clk) then if reset = '1' then --init stuff else for_loop: for i in 0 to n loop test_array_bit(i); end loop; end if; end if; end process; 

ZA-GENERATE

 for_generate: for i in 0 to n generate begin my_process: process(clk, reset) begin if rising_edge (clk) then if reset = '1' then --init stuff else test_array_bit(i); end if; end if; end process; end generate; 

What will be the impact on the implementation of FPGA and ASIC for these cases? What is easy to handle with CAD tools?

EDIT: Just adding the answer I gave to one helping guy to make my question clearer:

For example, when I ran a code snippet using for-loops in ISE, a summary summary gave me a fair result, taking a long time to figure out everything. when I transcoded my design, this time using for-generate and several processes, I used a little more area, but the tool was able to calculate everything faster, and my synchronization result was better. So, does this mean a rule that is always better to use for generating with the cost of an additional area and less complexity, or is this one of the cases when I have to check every possibility of implementation?

Answer 1

Assuming relatively simple logic in reset and test functions (for example, no interactions between adjacent bits), I expected both to generate the same logic.

Understand that since the entire for loop executes in a single clock cycle, the synthesis expands it and generates a separate instance of test_array_bit for each input bit. Therefore, it is entirely possible that synthesis tools can generate identical logic for both versions - at least in this simple example.

And on this basis, I would (slightly) prefer the for ... loop version, because it localizes the program logic, while the "generating" version globalizes it, placing it outside the process template. If you find the loop version a little easier to read, you will agree at some level.

However, this does not mean that it is dogmatic of style, and your experiment illustrates this: loop synthesis for lower equipment. Synthesis tools are complex and imperfect pieces of software, such as highly optimizing compilers, and share many of the same problems. Sometimes they skip the “obvious” optimization, and sometimes they perform complex optimization, which (for example, in software) is slower because its increased size broke the cache.

Therefore, it is preferable to write in the purest style where you can, but with some flexibility to work with the limitations of the tool and sometimes with real defects of the tool.

Different versions of tools remove (and sometimes introduce) such defects. You may find that the ISE option "use a new parser" (for parts up to Spartan-6) or Vivado or Synplicity gets this right where there is no ISE senior parser. (For example, signaling from procedures, older versions of ISE had serious errors).

It may be instructive to change the example and see if the synthesis can “get this right” (to produce the same equipment) for the simplest case and re-enter the complexity until it finds which design will fail.

If you find something specific in this way, it’s worth reporting it (answering your question). Xilinx used to encourage reporting such defects through its Webcase system; in the end they were even fixed! They seem to have stopped this, however, in the last year or two.

Answer 2

The first snippet will be equivalent to the following:

 my_process: process(clk, reset) begin if rising_edge (clk) then if reset = '1' then --init stuff else test_array_bit(0); test_array_bit(1); ............ test_array_bit(n); end if; end if; end process; 

While the second one generates processes n+1 for each i , together with the reset logic and everything (which may be a problem, since this logic will try to control the same signals from different processes).
In the general case, for loops are sequential statements containing sequential statements (i.e., each iteration is executed sequentially after the previous one). for-generate loops are parallel statements containing parallel statements, and that is how you can use it, for example, to create multiple instances of a component.